DapTechnology releases 1394/AS5643 IP for Microsemi IGLOO2 and SmartFusion2 FPGA devices

DapTechnology B.V. today announced the immediate availability of FireCore General Purpose Link (GPLink) for the Microsemi (now Microchip) IGLOO2 and SmartFusion2 FPGA devices.

The SAE AS5643 compliant FireCore GPLink IP Core is targeted at applications requiring a replacement for the currently used general purpose Link Layer Controller chips. FireCore GPLink has all functional blocks typically required for A&D implementations. Several markets can make use of the FireCore GPLink IP Core including Aerospace & Defense (A&D), Industrial, and Consumer Electronics. Examples of typical applications in A&D for the FireCore GPLink include remote I/O devices (RIO) and their standardized network interfaces (e.g. NDB, BIM, NIU).

FireCore also includes FireGate, a fully IEEE-1394b compliant PHY layer. Having FireGate connect and operate at S200 and S400 (the S100 version is to follow soon) marks a new milestone for the usage of IEEE-1394 in A&D as many current & upcoming programs can now leverage the FLASH-based FPGA benefits offered by the IGLOO2 and SmartFusion2 platforms together with the full-featured functionality of the FireGate PHY IP core.

Jeroen de Zoeten, DapTechnology’s Director of Engineering proudly adds: “FireCore is designed to be highly configurable. It allows for the pre-configuration of key functions and components via compilation parameters and the optimization of FPGA resources. For example, the number of PHY ports can be customized from 1 – 16, which is great for a wide variety of devices.”

The advantages of implementing a complete IEEE-1394 I/O interface with an IP solution can be summarized as:

  • Single-chip solution: Combination of  PHY and Link Layer IPs thus creating smaller footprint solutions. Additional components (CPUs, encoders, etc.) can be added to create a System On Chip (SOC) solution.
  • Flexible number of ports: Commercially available PHY chips typically have a fixed number (3) of ports. However, host adapters would likely benefit from 3 or more ports and a hub could even have more than that. For a PHY based on FPGA technology, the user can customize the number of ports as required.
  • Optional debug and test features: Optionally, the user can include debug and test features like BERT (Bit Error Rate Test) Low level data monitoring and recording
  • Field-upgradable: The used FPGAs are field upgradable thus allowing the addition new features or bug fixes, even if the device is already in the field.
  • Cost effective ASICS: Once a design is finalized an IP solution offers a very cost-effective path to the rendering of a custom ASIC.