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1394 and AS5643 IP Core solutions - FireCore Basic

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FireCore Basic

The FireCore Basic  is targeted for applications with up to S3200 data transmission requirements and for designs with a non-PCI Link Controller requirement. FireCore was designed to meet the general purpose and IIDC camera markets with higher speed and IEEE-1394-2008 Beta support not typically covered by other chip sets such as the Texas Instruments GP2Lynx (TSB12LV32). The FireLink Core therefore provides a seamless upgrade path to IEEE-1394-2008 Beta.

Targeted Applications

Several markets can make use of the FireCore Basic including Aerospace & Defense, Industrial, and Consumer Electronics. As a special option, AS5643 (Mil1394) protocol support is planned for FireCore Basic. While current implementations require significant host software support, FireCore will be able to support this layer with significantly better timing as well as reduced host resource utilization. Examples of typical applications in aerospace & defense for FireCore include command & control systems for space-based vehicles, missile guidance platforms, fighter aircraft flight control, as well as its implementation in avionics & IFE platforms for business and commercial aircraft.

The industrial applications of FireCore are quite broad and include robotics, machine vision, wide format digital printing and medical imaging. Finally, FireCore is ideal for use in Consumer Electronics equipment such as Set Top Boxes, DVD peripherals and High Definition A/V equipment.

Key features

  • Complete IP solution combining FireLink® Basic and FireGate
  • IEEE-1394-2008 Beta
  • Supports S100-S3200 transfer rates
  • Minimal Footprint
  • 1394b Link Layer supporting BOSS Arbitration
  • Scalable number of PHY ports from 1 to 16

Platform Availability

DapTechnology supports its IP cores on a wide variety of FPGA families. At the moment of writing the following platforms are supported but please don't hesitate to contact us for the very latest information:

  • Xilinx (Spartan, Artix, Kintex, Virtex, Zynq, ...)
  • Altera (Cyclone)
  • MicroSemi (IGLOO2, Smartfusion2)

 

Please contact DapTechnology directly to verify availability of specific functionality on your target platform!

Design features and benefits

There are several advantages when using FPGAs to implement a complete 1394 I/O interface. Some of these are:

  • Single-chip solution: Combination of PHY and Link Layer IPs thus creating smaller solutions. Additional components (CPUs, encoders, etc) can be added to create a System On Chip (SOC) solution.
  • Flexible number of ports: Commercially available PHY chips have a fixed number of ports which for small peripherals is often overkill. On the other hand, host adapters would likely benefit from 3 or more ports and a hub could even have more than that. For a PHY based on FPGA technology, the user can customize the number of ports as required.
  • Optional debug and test features: Optionally, the user can include debug and test features like BERT (Bit Error Rate Test), Low-level data monitoring and Recording.
  • Field-upgradable: The used FPGAs are field upgradable thus allowing the addition of new features or bug fixes, even if the device is already in the field.
  • Cost-effective ASICS: Once a design is finalized an IP solution offers a very cost-effective path to spinning a custom ASIC. 

Configurability

FireCore is designed highly configurable. We can preadjust key functions and components (speed, ports, target platforms, ...) as compilation parameters and so optimize the resources needed to meet customers needs. Such configuration parameter will be defined in close consultation with you so order to custom tailor the solution. Please note that due to differences within the various FPGA platforms certain functions might not be supportable on all target FPGAs. Please consult with our sales staff on availability.

Reference system

  • A complete Xilinx S3200 reference system is available, including a 4-lane PCI-express host adapter, an S3200 1394 analyzer and a peripheral development board which can be used by the customer to develop their products.
  • DapTechnology is currently working on a reference system for low speed (S100/S200/S400) Xilinx as well as Microsemi platforms.

FireCore Basic Details

Architecture

FireCore Basic combines the benefits of FireLink Basic and FireGate into one IP Core.

1394 and AS5643 IP Core solutions - FireCore Basic Block Diagram

FireLink® Basic consists of a fully IEEE-1394b-2008 compliant Link Layer implementation. All LLC related functional blocks ensure functional standards compliance as well as interoperability with off-the-shelf physical layer devices (assuming PHY layer I/O compliance).

Essential to FireLink® Basic is its very simple host connectivity. Via simple 32 bit data/address bus R/W operations as well as control registers. Updates can be handled via a dual-ported RAM or direct register access. Since any communication with this DPRAM is host processor driven this interface is optimized for small/medium sized data (isochronous, asynchronous and PHY layer) packets as well as low bandwidth requirements. Just like sending large amounts of data via the I/O bus, an increased number of individual bus transactions negatively affect the overall interface performance. For transmission and reception of large isochronous streams (e.g. video and/or audio) alternate data paths are available by means of the ISO Transmit and Receive Ports. They allow connecting dedicated data generating/processing hardware directly to the transmit/receive engines of FireLink®.  As these dedicated ports are bypassing the host main processor they are not restricted by performance limitations of the main host interface and therefore guarantee optimized data rates.

An additional benefit is the ability to customize several functional elements of the core. Since not all 1394 implementations require a full-featured 1394 interface (e.g. a pure IPv4 (IP over 1394) or AS5643 implementation using only asynchronous messaging can reduce FPGA footprint requirements by leaving out certain functional blocks like isochronous data ports, Cycle Timer and transmit, etc. from the deployed netlist. Likewise, an isochronous data transmitting video camera can omit a RX iso port as it is a dedicated data streaming device and the general purpose RX and TX buffer can be held small.

FireGate is a fully IEEE-1394b-2008 compliant PHY Layer implementation. The main PHY layer related functional blocks ensure functional standard compliance as well as interoperability with off-the-shelf physical layer devices.

A key element of FireGate is its configurable PHY front end, i.e. the ability to customize several aspects of the PHY cable environment interface. During the configuration phase the total number of available PHY ports can be adjusted (max 16) as well as the total number of PHY instances per FPGA device. Furthermore, the speeds supported by the PHY can be defined. The PHY speeds can be either predefined to support single network speeds (for example S100, S200, S400, ...). This reduces network speed negotiation times (only applicable if the entire network would use the same PHY). Alternatively, the PHY(s) can be configured to support speed ranges (e.g. S200 - S800) and limit the speed negotiation to those values).

Additionally, the PHYs also contain patented improvements over standard 1394 implementations. DapTechnology has been one of the very first companies to actively advocate such functionalities within PHY devices.

Data Exchange Mechanism

In FireLink® Basic the packet data flow is processor driven, i.e. any received/transmitted packets have to be read from or written to a Dual-Ported RAM Buffer by a processor. The Dual Port RAM Buffer is located inside the core and is customizable in size to accommodate for the maximum packet size. This concept is intended for small core sizes.

Packets to be transmitted are written into the Isochronous or Asynchronous Transmit Buffer.

Isochronous packets can also be transmitted from the Isochronous Transmit Port.

Received Packets are stored in the Isochronous or Asynchronous Receive Buffer or are routed to an Isochronous Receive Port or the Asynchronous Receive Port.

FireCore Basic media files

Product Image(s)

1394 and AS5643 IP Core solutions - FireCore Basic Demo setup
FireCore Basic Demo setup

Demo setup used at VISION 2009 in Stuttgart, Germany. Setup successfully demonstrated video streaming at S3200 via a 10m 1394b cable. See the press release for more details.

Press release

FireCore Basic documentation

  

FireESDK Embedded Development Kit Datasheet

Download full FireESDK datasheet as a PDF

  

Manual & Design Guideline

Available under NDA only.
Please send an email to sales(at)daptechnology.com for more information.

FireCore Basic sales info

FireCore Basic License Types

FireCore Basic NetList
Development License

Status: active
P/N: FCB-NET-REF
Codes: ECCN: 3D991,  HST: N/A

FireCore Basic Source Code
Development License

Status: active
P/N: FCB-SRC-REF
Codes: ECCN: 3D991,  HST: N/A

FireCore Basic Deployment
Deployment License

Status: active
P/N: FCB-DEP-[VOL/TERM]
Codes: ECCN: 3D991,  HST: N/A

Warranty (IP)

Standard: 12 months, limited.

Options: Additional 1-year Support packages may be purchased.

Support

All IP products will be supported on a 24 hours response basis and free of charge during the warranty period. For support questions please contact: sales(at)daptechnology.com

Of course you can also call us during our office hours from 9:00 until 17:00 hours (GMT +1:00). Contact Info

Price Info / Quote Request

Please contact sales(at)daptechnology.com for current pricing.

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USA Representatives

For the U.S.A., we have as representatives:

Representative Territory Phone URL
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