FireCore - Basic - Extended - GPLink

The most advanced and thoroughly tested 1394
and AS5643 solutions in the market.

FireCore -
PHY and Link functionality in one package

FireCore is a synthesizable IEEE-1394-2008 Beta PHY and Link Layer Controller (LLC) Core integrated into a single IP product. FireCore combines the PHY and Link Layer requirements of a typical 1394 device in one IP Core. Based on FireGate PHY IP core and FireLink® LLC IP core, FireCore is architected to support data rates of S100 through S3200 and various host interfaces including general purpose, OHCI and OHCI with AS5643 options. System designs can now entirely isolate the typical issues associated with off-the-shelf silicon (availability, road-map, revisions) and have full control via in-field upgrades and optimization.

The advantages are obvious: Apart from having achieved new milestones for S1600 and S3200 transmission speeds, FireCore offers a very customizable solution for both the Link as well as the PHY layer. Key elements include a configurable number of PHY ports, Bit Error Injection, a configurable host interface with DMA capability, optional features like Bus, Resource and Cycle Master capabilities, expanded hardware filtering and isochronous data streaming ports.

With FireCore DapTechnology targets two main market segments, i.e. high-bandwidth and AS5643 applications, the latter is predominant in Aerospace and Defense systems.

Faster speeds (beyond 800Mb/s) for 1394 have become a real need. The requirement predominantly originates from bandwidth-rich applications in the video and audio arena. Even with the current industry standard of 800Mb/s there are restrictions in the amount of video data that can be transmitted, especially when dealing with high-resolution, uncompressed video streams. While quite common and generally accepted in the consumer video arena (MPEG or DV video compression) in virtually all industrial, medical, scientific and avionics applications, lossy compression (e.g. JPEG) algorithms are not usable. Higher and higher video resolutions demand more and more bandwidth for video streams. Likewise, the number of simultaneously transmitted streams is rising for typical applications. DapTechnology is firmly convinced that FireCore is the only viable solution that offers a technological and economical road-map for products in this domain and therefore presents a bright future for next generation vision-based products.

The other key area for value added deployment of FireCore is the field of highly targeted applications. Usage of 1394 in the aerospace market is a prime example. DapTechnology’s new FireCore package offers unprecedented technical features and functions, added flexibility, options for customization and future expansion. The product not only addresses the earlier mentioned silicon availability and road-map issues but furthermore, it offers a road-map for AS5643 hardware level support. Together with FireStack® (DapTechnology’s 1394 software stack), FireCore is designed to take complete advantage of AS5643 extensions. It is the clear objective to fully abstract the 1394 protocol layer and largely the AS5643 protocol layer so the implementers can focus entirely on system-level functions like fault tolerance, fault isolation and redundancy. For both firmware components – FireLink® and FireGate® - DapTechnology has a very clear strategic vision as to how the company directly supports distinct features and functions for AS5643 (Mil1394). Both can be implemented as standalone solutions with remarkable advantages. In combination the two offer the possibility to architect a system with measurable benefits.

Three powerful flavors

FireCore® is available in three distinct variants:

FireCore Basic:  a) Processor driven data exchange (RX/TX to DPRAM) ideal for non-OHCI and non-GP2Lynx-alike designs, Mil1394 enhancements, optimized for minimal footprint and resource utilization, b)1394b PHY layer (FireGate)

FireCore Extended:  a) DMA-driven data transfer, ideal for OHCI and Extended OHCI functionality, Mil1394 enhancements, optimized for high-bandwidth throughput, b)1394b PHY layer (FireGate)

FireCore GPLink:   replacement for TI GP2Lynx when used in typical AS5643 device systems and paired with 1394b PHY layer (FireGate)

FireCore uses the same PHY IP - FireGate - with all three Link layer variants. As FireGate resembles a highly adaptable and customizable component, any variant of FireCore can be fine tuned and modified to meet specific project and program requirements. Please make sure that you speak to our product specialists to identify your specific needs.

Common Features

Host Bus Interface

  • Generic: A generic 32-bit synchronous host bus.
  • OPB: A 32-bit synchronous bus used in Xilinx FPGAs for their MicroBlaze and PowerPC processors.
  • PLB: An internal bus used in Xilinx FPGAs for their MicroBlaze and PowerPC processors.
  • AXI4: An internal bus used in FPGAs for their internal processors.
  • Avalon: A 32-bit synchronous bus used in Altera FPGAs for their NIOS processor.

The Basic version is implemented as a slave-only bus interface while the Extended version will utilize a DMA engine which will access the bus as a Master.

Control Status
Both versions have a number of registers that can be written and or read. They are used to control the Link Layer Controller and to check its status. For the Extended version, control for the DMA engine is also provided.

CRC Calculation/Verification
Data and Header CRC are automatically added for outgoing packets. CRCs are verified for incoming packets. Faulty packets are ignored. Additionally errors can be injected for transmitted packets (header and or data CRC, VPC).

Ack Generation
Acknowledge Packet Generation is based on incoming packet content, available buffer space as well as LLC state. As an added feature Acknowledges can be suppressed or erroneous Ack codes can be injected.

NodeID (async) and channel number (iso) specific packet filter engine.

Cycle Start Generation (optional)
A Cycle Start Packet generation functionality with its associated Cycle_Time Register is optionally supported by the hardware.

ISO Ports (optional)
Optionally, ISO Receive and/or ISO Transmit ports can be added. The purpose of these ports is to connect dedicated stream hardware (e.g.: image/video generating/receiving hardware) for the handling of data streams without burdening the host processor. Received and transmitted isochronous packets can be routed through the ISO Ports therefore providing a dedicated and highly efficient data path for the isochronous packets. Optionally, the packet headers will be skipped (RX) or automatically generated (TX).

Monitor (optional)
Optionally, a packet monitor is supported. This tool is mainly targeted for debugging purposes.