FireLink® - Basic - Extended - GPLink

Three IP_LLC variants providing the right solutions
for any IEEE-1394 and AS5643 integration challenge!

FireLink® LLC IP Core

The synthesizable IEEE-1394-2008 Beta Link Layer Controller (LLC) Core, FireLink®, is based on the Link Layer Controller that has been used for several years in the FireSpy® analyzer products by DapTechnology. FireLink® is a mature core that has been implemented in Xilinx, Altera and Microsemi FGPAs. FireLink® is offered in three configurations, i.e. Basic, Extended and GPLink.

As a special option, the FireLink LLC (Extended only) offers firmware support for the AS5643 protocol. While current implementations require significant host software support, FireLink® with AS5643 support off-loads the host software requirements by making the hardware AS5643 timing-aware which produces significantly better timing as well as reduced host resource utilization. Examples of typical applications in aerospace & defense for the FireLink® include command & control systems for space-based vehicles, missile-guidance platforms, fighter-aircraft flight-control, as well as its implementation in avionics & IFE platforms for business and commercial aircraft.



Three powerful variants

FireLink® is available in three distinct variants:

FireLink® Basic:  Processor-driven data exchange (RX/TX to DPRAM) ideal for non-OHCI and non-GP2Lynx-alike designs, Mil1394 enhancements, optimized for minimal footprint and resource utilization

FireLink® Extended:  DMA-driven data transfer, ideal for OHCI and Extended OHCI functionality, Mil1394 enhancements, optimized for high-bandwidth throughput

FireLink® GPLink:  Replacement for commercially available general purpose chips when used in typical AS5643 device systems

Common Features

Host Bus Interface

  • Generic: A generic 32-bit synchronous host bus.
  • OPB: A 32-bit synchronous bus used in Xilinx FPGAs for their MicroBlaze and PowerPC processors.
  • PLB: An internal bus used in Xilinx FPGAs for their MicroBlaze and PowerPC processors.
  • AXI4: An internal bus used in FPGAs for their internal processors.
  • Avalon: A 32-bit synchronous bus used in Altera FPGAs for their NIOS processor.

The Basic version is implemented as a slave-only bus interface while the Extended version will utilize a DMA engine which will access the bus as a Master.

Control Status
Both versions have a number of registers that can be written and or read. They are used to control the Link Layer Controller and to check its status. For the Extended version, control for the DMA engine is also provided.

CRC Calculation/Verification
Data and Header CRC are automatically added for outgoing packets. CRCs are verified for incoming packets. Faulty packets are ignored. Additionally errors can be injected for transmitted packets (header and or data CRC, VPC).

Ack Generation
Acknowledge Packet Generation is based on incoming packet content, available buffer space as well as LLC state. As an added feature Acknowledges can be suppressed or erroneous Ack codes can be injected.

NodeID (async) and channel number (iso) specific packet filter engine.

Cycle Start Generation (optional)
A Cycle Start Packet generation functionality with its associated Cycle_Time Register is optionally supported by the hardware.

ISO Ports (optional)
Optionally, ISO Receive and/or ISO Transmit ports can be added. The purpose of these ports is to connect dedicated stream hardware (e.g.: image/video generating/receiving hardware) for the handling of data streams without burdening the host processor. Received and transmitted isochronous packets can be routed through the ISO Ports therefore providing a dedicated and highly efficient data path for the isochronous packets. Optionally, the packet headers will be skipped (RX) or automatically generated (TX).

Monitor (optional)
Optionally, a packet monitor is supported. This tool is mainly targeted for debugging purposes.