U.S. Patent 9,575,866 on "Diagnostic Module for Monitoring Electric Data Transmission" (issued on Feb.21, 2017) describes a Sub-Diagnostic Module incorporated into a System Module. The Sub-Diagnostic Module receives signals from the System Modules through the diagnostic signal interface. The diagnostic signal interface passes the signals through to the diagnostic signal evaluation logic where it determines if a signal or combination of signals is an event to be recorded in the sub-diagnostic registers and/or the sub-diagnostic log memory. The events recorded in the registers and log memory are accessed by the Portable Diagnostic Module through the Sub-Diagnostic Module's diagnostic protocol interface. Recorded events placed in log memory are synchronized by the sub-diagnostic time synchronizer. The time synchronizer receives high resolution time information from a local clock, such as a physical layer clock, and lower resolution network synchronized information from the diagnostic protocol interface.
U.S. Patent 9,602,302 on "Method for disabling a Legacy Loop Detect Circuit in a Beta Node" (issued on Feb.27, 2017) describes a method for disabling or removing a Legacy loop detect circuit to eliminate the circuit erroneously detecting a legacy loop during a IEEE-1394 serial bus initialization. The method includes providing a programmable code to the Legacy loop detect circuit for increasing a reset count to a value greater than three (3) to the Legacy loop circuit thus reducing the probability of an erroneous disconnect of a Beta node connection. This method provides for more robust Beta loop node operation during high frequency bus resets.
U.S. Patent 9,747,186 on "Method for blocking bus resets in a IEEE-1394 high-performance serial bus" (issued on Aug.29, 2017) describes a method of delaying or blocking new bus resets from propagating while a previous bus initialization (bus reset, tree-id or self-id) is in process during the performance of a IEEE-1394 serial bus. The method provides for more robust Beta only bus operation during high frequency bus resets. The bus resets are caused by noise events, power-up and power-down sequences and other bus reset causing events.
DapTechnology has also applied for other patent applications with the USPTO:
- IEEE1394 Beta Fast Reconnect. It defines a method for testing if a connection between two nodes has been physically broken or has temporarily been lost due to a loss of synchronization. Furthermore, the invention provides a fast reconnect method, that attempts one or more times to determine a temporary disconnect with a range of microseconds to milliseconds in which a temporary disconnect shall be verified. Also, the number of attempts for this reconnect can be replaced by a certain time period. This application is currently under review by the USPTO and a patent award is pending.
- portErrorMonitor Enhancement. It defines a method for improving the stability of the IEEE-1394 bus if a port receives corrupted characters/ Such corruption can result from EMI spikes or similar events which are known to adversely affect the signal integrity on the bus. The method describes how an extension of PHY registers can be used to customize the threshold verification limit or portError and therefore allows adjustment of the Loss-of-Synchronization transition. This application is currently under review by the USPTO and a patent award is pending.
All patent awards and applications affirm the company's leading position in IEEE-1394 and AS5643 technology and its continued quest to develop leading edge solution. Furthermore, the awards honor three essential components in the company's growing pool of technology components. DapTechnology spends considerable efforts in improving key technology elements for AS5643 and IEEE-1394 in order to improve network stability and reliability in deterministic avionics control systems. The now patented technologies are or will be incorporated in several products from DapTechnology.