FireLink® Extended Version

The Extended Core is targeted for applications with up to 800 Mbps data transmission requirements and high data throughput requirement. Typically such high bandwith data rates are accomplished via DMA operations. Currently, there is no such silicon available for non PCI buses. The FireLink® Core was designed to fill this gap and features an OHCI like descriptor model

Some markets that could leverage the DapTechnology Firelink Core are Aerospace & Defense, Industrial, and Consumer Electronics. As a special option, the FireLink® LLC offers Firmware Support for the SAE5643 (Mil1394) protocol. While current implementations require significant host SW support the FireLink can support this layer with significantly better timing as well as reduced host resource utilization. Typical examples of applications in aerospace & defense for the Firelink® would include command & control systems for space-based vehicles, missile platforms, and fighter aircraft, as well as its implementation in avionics & IFE platforms for business and commercial aircraft.

The industrial applications of Firelink® are quite broad and include robotics, machine vision, wide format digital printing and medical imaging. Finally, the FireLink LLC Core is ideal for use in Consumer Electronics equipment such as Set Top Boxes, DVD peripherals and High Definition A/V equipment.

In the Extended version the packet data flow is DMA driven. The LLC’s DMA Engine handles the transfer to/from a FIFO Buffer for receiving and sending packets automatically, enabling high bandwidth systems. The user creates lists of packets to be sent and/or cyclic buffers for packets to be received. The FIFO is located inside the core and its size is customizable to accommodate host bus latency

This concept is ideal for high traffic bandwidth.

Host Bus Interface
•Generic: A generic 32-bit synchronous host bus.
• OPB: A 32-bit synchronous bus used in Xilinx FPGAs for their MicroBlaze and PowerPC processors.
• Avalon: A 32-bit synchronous bus used in Altera FPGAs for their NIOS processor.

The Basic version is implemented as a slave-only bus interface while the Extended version, however, will utilize a DMA engine which will access the bus as a Master.

Control Status
Both versions have a number of registers that can be written and or read. They are used to control the Link Layer Controller and to check its status. For the Extended version, control for the DMA engine is also provided.

CRC Calculation/Verification
Data and Header CRC are automatically added for Outgoing Packets. CRCs are verified for incoming packets. Faulty packets are ignored. Additionally errors can be injected for TX packets (header and or data CRC).

Ack Generation
Acknowledge Packet Generation is based on incoming packet content, available buffer space as well as LLC state. As an added feature Acknowledges can be suppressed or erroneous Ack codes can be injected.

Filtering
NodeID (async) and channel number (iso) specific packet filter engine.

Cycle Start Generation (optional)
A Cycle Start Packet generation functionality with its associated Cycle_Time Register is optionally supported by the HW.

ISO Ports (optional)
Optionally, ISO Receive and/or ISO Transmit ports can be added. The purpose of these ports is to connect dedicated stream HW (e.g.: image/video generating/receiving HW) for the handling of data streams without burdening the host processor. Received and Transmitted isochronous packets can be routed through the ISO Ports therefore providing a dedicated and highly efficient data path for the isochronous packets. Optionally the packet headers will be skipped (RX) or automatically generated (TX).

Monitor (optional)
Optionally, a packet monitor is supported. This tool is mainly targeted for debugging purposes.