FireGate - 1394B PHY Layer IP Core
With its latest product development efforts DapTechnology again sets an example for industry leadership and a keen technology vision. When entirely finished FireGateTM is going to complement DapTechnology’s successful series of intellectual property (IP) solutions. Not only will DapTechnology offer its industry proven Link layer IP solution FireLink® but also add the complex PHY layer with transmission speeds up to S3200 to its product portfolio. And when paired the two individual products can be combined into one single FPGA as FireCoreTM, i.e. a fully integrated field programmable system-on-the-chip (SOC) solution that clearly aims to take the integration of 1394b to the next level.
Faster speeds (beyond 800 Mb/s) for FireWire have become a real need. The need predominantly originates from bandwidth rich applications mainly in the video and audio arena. Even with the current industry standard of 800 Mb/s there are restrictions in the amount of video data that can be transmitted, especially when dealing with high-resolution, uncompressed video streams. While quite common and accepted on the consumer video arena (MPEG or DV video compression) in pretty much all industrial, medical, scientific and avionics applications lossy compressions algorithms are not usable and the size of video data streams is constantly increasing. Adequately the number of simultaneously transmitted streams is rising as well for typical applications.
Over the years DapTechnology has established itself as an industry leader for FireWire related IP solutions and has gained experience with the specifics of FireWire PHY technology during the development of the InvisiPHY® technology which resulted in the unique FireStealth® analyzer and related IP solutions. And leveraging on this experience Dap had launched the development of a Beta-only FireWire PHY solution FireGateTM and successfully established means to utilize the Transceivers inside modern FPGAs. Such an approach has resulted not only in high speed abilities (800Mb/s (S800), 1600Mb/s (S1600) or 3200Mb/s (S3200)) but also in quite interesting expansion capabilities as required for aerospace and industrial applications.
Status: in development
Planned Release: Q1 2011
Status: in development
Planned Release: Q4 2011
DESIGN FEATURES AND BENEFITS:
There are several advantages when using FPGAs to implement a PHY. Some of these are:
Single-chip solution: The PHY IP can be combined with Link Layer IPs, creating smaller solutions. Additional components can be added to create a System On Chip (SOC) solution.
Flexible number of ports: Commercially available PHY chips have a fixed number of ports. Small peripherals from having only one or two ports. Host adapter would likely benefit from 3 or more ports and a hub could even have more than that. For a PHY based on FPGA technology, the user can customize the number of ports as required.
Optional debug and test features: Optionally the user can include debug and test features like BERT (Bit Error Rate Test) Low level data monitoring and recording
Field-upgradable: The used FPGAs are field upgradable thus allowing to add new features or fix bugs, even if the device already in the field.
Cost effective ASICS: Once a design is settled an IP solution offers a very cost effective path to spinning a custom ASICS.
Dap is developing a complete S3200 system, including a 4-lane PCI-express host adapter, an S3200 FireWire analyzer and a peripherals development board which can be used by the customer to develop their products.