FireLink® Verification and Testbench

FireLink® Verification Model Example

DapTechnology’s FireLink® IP core includes a state-ofthe-art verification and simulation suite. The entire product has been developed using stringent test criteria and procedures which are applied in all different stages, i.e. design, simulation and actual implementation.

FireLink® Testbench

A special VHDL Testbench has been developed and is made available to our customers for their own test and verification tasks. It mainly targets the host emulation, the LLC layer and the PHY Emulation. Test vectors (I/O files) can be used to stimulate these segments independently.

 
•    Automated transaction based system simulation
•    Easy to use pass/fail reporting
•    Detailed analysis possibility presenting waveforms and signals
•    RTL level functional/behavioral simulation
•    Post synthesis, Netlist level functional/behavioral simulation
•    Post place and route, Netlist level timing simulation possibility
•    Test bench implementation done by people not involved in the implementation of the actual design