FireSpy® Bus Analyzers

Advanced I/O Solutions

1394 Interface Solutions

Test&Verification Sol.

1394b IP Solutions

AS5643 Dev.Suite



Services and Consulting


Demo Downloads

FireGate - IEEE-1394-2008 Beta PHY Layer IP Core

FireGate is a standalone synthesizable IEEE-1394-2008 Beta PHY Layer IP Core. FireGate can be connected to any IEEE-1394-2008 Beta Link Layer Controller or when integrated with DapTechnology’s FireLink® it becomes FireCore™, i.e. a fully integrated field programmable system-on-the-chip solution that clearly aims to take the integration of 1394 to the next level. FireGate is designed to operate at data rates up to S3200 and is scalable from 1 to 16 ports. While FireGate is architected to support S100 through S3200, the targeted FPGA dictates which speeds can be supported. For example the S1600 version of the IP is implemented in an FPGA, see the DapTechnology HAC1600 for details, that supports S800 and S1600 while the S3200 version is implemented in an FPGA that supports S400, S800, S1600 and S3200.

Faster speeds (beyond 800 Mb/s) for FireWire have become a real need. The need predominantly originates from bandwidth rich applications mainly in the video and audio arena. Even with the current industry standard of 800 Mb/s there are restrictions in the amount of video data that can be transmitted, especially when dealing with high-resolution, uncompressed video streams. While quite common and accepted on the consumer video arena, MPEG or DV video compression, other markets such as industrial, medical, scientific and avionics applications cannot tolerate lossy compression algorithms and therefore much high bandwidth is required. In addition the number of simultaneously transmitted video/audio streams is also increasing.


S400 Status: active
Partnumber: PHY400-RPL
S800-S1600 Status: active
Partnumber: PHY1600-RPL
S800-S32000 Status: active
Partnumber: PHY3200-RPL
S100-S32000 Status: under development
Partnumber: PHY100-3200-RPL

Design features and benefits

There are several advantages when using FPGAs to implement a PHY. Some of these are:

Single-chip solution: The PHY IP can be combined with Link Layer IPs, creating smaller solutions. Additional components can be added to create a System On Chip (SOC) solution.

Flexible number of ports: Commercially available PHY chips have a fixed number of ports. Small peripherals from having only one or two ports. Host adapter would likely benefit from 3 or more ports and a hub could even have more than that. For a PHY based on FPGA technology, the user can customize the number of ports as required.

Optional debug and test features: Optionally the user can include debug and test features like BERT (Bit Error Rate Test) Low level data monitoring and recording

Field-upgradable: The used FPGAs are field upgradable thus allowing to add new features or fix bugs, even if the device already in the field.

Cost effective ASICS: Once a design is settled an IP solution offers a very cost effective path to spinning a custom ASICS. 

Reference system

Dap has developed a complete S3200 system, including a 4-lane PCI-express host adapter, an S3200 FireWire analyzer and a peripherals development board which can be used by the customer to develop their products.

 © 1998-2017 DapTechnology